1. Field of the Invention
The present invention relates to a DRAM cell, and more particularly, to a DRAM cell having independent and asymmetric source/drain regions and a method of forming the same.
2. Description of the Prior Art
Recently, the interval between source and drain junctions is getting gradually smaller as the integrity of DRAM devices is exceeding 1-giga bytes. This creates leak current from the source junction to the drain junction due to punch-through while decreasing the electric potential difference between the source and drain junctions. Although ion injection is performed in order to restrain punch-through, excessive ion injection creates a high value of electric field to the junctions, thereby creating leakage current. Accordingly, it is difficult to obtain refresh time in such an amount necessary for the operation of a DRAM device.
FIG. 1 is a sectional view illustrating a structure of a DRAM cell of the prior art. Referring to FIG. 1, a conventional DRAM cell fabrication process includes: forming a device isolation film 11 in a proper area of a semiconductor substrate 10; injecting well ion; and forming an ion injection layer for preventing punch-through and a channel ion injection layer 13 for adjusting threshold voltage. After sequentially forming a gate oxide film 14, gates 15 and a hard mask layer 16, the conventional process forms a gate spacer 17, and source/drain junctions 20 and 21. Then, the conventional process includes forming contact plugs 18, which respectively contact with the source/drain junctions.
In the conventional fabrication process shown in FIG. 1, the gate-forming step is collectively performed using the gate mask once and the ion injection step for forming the source/drain junctions is also collectively performed without discrimination of the source junctions from the drain junctions. In particular, for the purpose of decreasing junction electric field and prolonging refresh time, source/drain ion injection is so performed with weight to the source junctions, which have a relatively more important function, that the junctions have a thick and circular lateral configuration.
However, because the drain junction 21 is also formed thick and wide as well as the source junctions 20, leakage current (as indicated with an arrow B in FIG. 1) takes place due to punch-through between the source/drain junctions thereby shortening refresh time. Although ion is injected to restrain punch-through, an ion injection layer 12 for restraining punch-through has a polarity value different from that of the source/drain junctions 20 and 21, thereby increasing electric field of the junctions (A in FIG. 1) to create resultant leakage current and further shorten refresh time.
Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a DRAM cell and a fabrication method thereof capable of ensuring refresh characteristics in a highly integrated DRAM cell transistor by realizing a source/drain structure which can remarkably decrease leakage current due to high electric field and punch-through between the source/drain junctions.
In order to accomplish this object, the present invention provides a DRAM cell having source/drain regions, which are separately formed to have an asymmetric structure via ion injection steps independent from each other.
According to an aspect of the invention for realizing the above objects, a DRAM cell comprises: a device isolation film for defining an active region on a semiconductor substrate; a well region formed inside the semiconductor substrate corresponding to the active region; a channel layer overlying the well region; a field stop layer underlying the well region; a plurality of gates on the semiconductor substrate; source and drain junctions respectively formed between the gates inside the semiconductor substrate, the source and drain junctions having an asymmetric junction structure; and contact plugs respectively contacting with the source and drain junctions. In particular, the source junctions are thick and the drain junction is thin so that they have an asymmetric configuration.
The DRAM cell comprise of the invention may further comprises source and drain spacers formed on upper and lateral faces of the gates, wherein the source spacer is thicker than the drain spacer, and selectively formed on the lateral faces of the gate adjacent to the source junctions. Also, the DRAM cell comprise of the invention may further comprise a channel layer overlying the well region and a field stop layer underlying the well region.
According to another aspect of the invention for realizing the above objects, a fabrication method of a DRAM cell comprises the following steps of: forming a device isolation film for defining an active region on a semiconductor substrate; forming a well region inside the semiconductor substrate corresponding to the active region; depositing gate material on a resultant structure and forming gates using a first gate mask, which selectively exposes portions of the resultant structure corresponding to source regions; removing the first gate mask and forming source junctions inside the semiconductor substrate so that the source junctions have a smooth and thick lateral configuration; selectively etching the gates using the second gate mask, which selectively exposes a portion of the resultant structure corresponding to a drain region, and forming a drain junction inside the semiconductor substrate so that the drain junction has a relatively thin lateral configuration compared to the source junctions; removing the second gate mask, depositing an interlayer insulation film, and selectively etching the interlayer insulation film to expose the source junctions and the drain junction; and forming contact plugs respectively contacting with the source junctions and the drain junction.
The fabrication method of a DRAM cell of the invention may further comprise the steps of: depositing a source spacer after the step of removing the first gate mask and forming source junctions; and depositing a drain spacer relatively thinner than the source spacer on the entire surface of a resultant structure after the step of removing the second gate mask, wherein the step of selectively etching the gates using the second gate mask comprises selectively etching the source spacer, and wherein the step of selectively etching the interlayer insulation layer comprises selectively etching the source spacer and the drain spacer, and after the step of forming the well region, forming the field stop layer at a proper depth inside the semiconductor substrate and a channel layer in the vicinity of the semiconductor substrate.